// ******************************************************************************
// Copyright     :  Copyright (C) 2016, Hisilicon Technologies Co. Ltd.
// File name     :  cpi_dfx_glb_reg_offset.h
// Project line  :  IT产品线
// Department    :  图灵ICT处理器开发部
// Author        :  xxx
// Version       :  V100
// Date          :  2014/5/8
// Description   :  Hi 1822 is a throughput of 100Gbps CNA chip. It provide large bandwith, low latency, scalability
// converged network solution, support network convergency, virtualization, protocol offload, and serves IT product and
// CT product. Others        :  Generated automatically by nManager V4.0.2.5 History       :  xxx 2016/10/25 15:05:13
// Create file
// ******************************************************************************

#ifndef CPI_DFX_GLB_REG_OFFSET_H
#define CPI_DFX_GLB_REG_OFFSET_H

/* CPI_DFX_GLB Base address of Module's Register */
#define HI1822_CPI_DFX_GLB_BASE (0x41af000)
#define CPI_DFX_TYPE_GLB (0x0)

/* **************************************************************************** */
/*                      HI1822 CPI_DFX_GLB Registers' Definitions                            */
/* **************************************************************************** */

#define HI1822_CPI_DFX_GLB_GLB_DEBUG_CFG_REG (HI1822_CPI_DFX_GLB_BASE + 0x0) /* CPI debug control */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_MRD_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x4) /* CPI debug Rx Mrd TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_MWR_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x8) /* CPI debug Rx Mwr TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_CPL_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0xC) /* CPI debug Rx CPL/CPLD TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_DBL_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x10) /* CPI debug Rx UR Mrd TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_DWQE_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x14) /* CPI debug Rx UR Mrd TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_ESL__TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x18) /* CPI debug Rx others TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_DEBUG_RX_BAR_HIT6_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x1C) /* CPI debug Rx BAR hit == 6 TLP counter */
#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x400) /* CPI BP WATCH Status */
#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_WINDOW_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x404) /* CPI backpressure watch window */
#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_BITMAP_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x408) /* CPI backpressure watch bitmap */
#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_START_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x40C) /* CPI backpressure watch start */
#define HI1822_CPI_DFX_GLB_GLB_CPI_BP_WATCH_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x410) /* CPI backpressure watch counter */
#define HI1822_CPI_DFX_GLB_GLB_CSR_TIMEOUT_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x414)
#define HI1822_CPI_DFX_GLB_DWQE_API_NO_ENOUGH_DATA_REG (HI1822_CPI_DFX_GLB_BASE + 0x418)
#define HI1822_CPI_DFX_GLB_DWQE_DBL_NO_ENOUGH_DATA_REG (HI1822_CPI_DFX_GLB_BASE + 0x41C)
#define HI1822_CPI_DFX_GLB_NORM_DBL_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x420)
#define HI1822_CPI_DFX_GLB_NORM_DBL_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x424)
#define HI1822_CPI_DFX_GLB_DWQE_DBL_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x428)
#define HI1822_CPI_DFX_GLB_DWQE_API_TX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x42C)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_MSK_REG (HI1822_CPI_DFX_GLB_BASE + 0x430)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_CNT_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x434)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_ON_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x438)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_BP_OFF_PORT_REG (HI1822_CPI_DFX_GLB_BASE + 0x43C)
#define HI1822_CPI_DFX_GLB_DWQE_REQ_BUF_BGN_REG (HI1822_CPI_DFX_GLB_BASE + 0x440)
#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_IN_TX_REG (HI1822_CPI_DFX_GLB_BASE + 0x444)
#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_NO_BUF_REG (HI1822_CPI_DFX_GLB_BASE + 0x448)
#define HI1822_CPI_DFX_GLB_DWQE_DBL_WITHOUT_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x44C)
#define HI1822_CPI_DFX_GLB_DWQE_TX_DBL_AFTER_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x450)
#define HI1822_CPI_DFX_GLB_DWQE_NO_DBL_AFTER_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x454)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_OVERWRITE_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x458)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_AGING_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x45C)
#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_PUSH_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x460)
#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_POP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x464)
#define HI1822_CPI_DFX_GLB_DWQE_TX_REQ_FIFO_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x468)
#define HI1822_CPI_DFX_GLB_CPI_DPATH_O_FSM_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x46C)
#define HI1822_CPI_DFX_GLB_CPI_DPATH_O_CNT_TYPE_REG (HI1822_CPI_DFX_GLB_BASE + 0x470)
#define HI1822_CPI_DFX_GLB_DWQE_DROPPING_INVLD_REG (HI1822_CPI_DFX_GLB_BASE + 0x474)
#define HI1822_CPI_DFX_GLB_DWQE_SW_FORCE_DROP_REG (HI1822_CPI_DFX_GLB_BASE + 0x478)
#define HI1822_CPI_DFX_GLB_ICTL_DBL_REQ_SOP_NULL_REG (HI1822_CPI_DFX_GLB_BASE + 0x47C)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x480)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x484)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x488)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_CNT_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x48C)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x490)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x494)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x498)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x49C)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A0)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A4)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_SOP_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x4A8)
#define HI1822_CPI_DFX_GLB_DPATH_O_DMA_EOP_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x4AC)
#define HI1822_CPI_DFX_GLB_CEQ_CI_SW_WR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B0)
#define HI1822_CPI_DFX_GLB_AEQ_CI_SW_WR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B4)
#define HI1822_CPI_DFX_GLB_CEQ_TX_INT_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4B8)
#define HI1822_CPI_DFX_GLB_AEQ_TX_INT_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4BC)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_WR_PCIE_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C0)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_WR_UCPU_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C4)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_RD_PCIE_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4C8)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_RD_UCPU_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4CC)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_OSCH_CPL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D0)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_ICTL_CPL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D4)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_APICTL_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4D8)
#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_AEQE_TO_DST_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4DC)
#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_AEQE_TO_SRC_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E0)
#define HI1822_CPI_DFX_GLB_CPI_PCIE_MB_STAT_TO_SRC_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E4)
#define HI1822_CPI_DFX_GLB_CPI_UCPU_MB_AEQE_TO_DST_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4E8)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_AEQ_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4EC)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_CEQ_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F0)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_API_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F4)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_CSR_INTCTL_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4F8)
#define HI1822_CPI_DFX_GLB_CPI_IPUSH_UPITF_CLP_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x4FC)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR0_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x500) /* CPI internal RAM ECC error injection */
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x504)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x508)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x50C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x510)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x514)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x518)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_INJ_ERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x51C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x520)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x524)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x528)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x52C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x530)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x534)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x538)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x53C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x540)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x544)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x548)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x54C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x550)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x554)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x558)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x55C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x560)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x564)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x568)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x56C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x570)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x574)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x578)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x57C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_ERR_ADDR8_REG (HI1822_CPI_DFX_GLB_BASE + 0x580)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR0_REG (HI1822_CPI_DFX_GLB_BASE + 0x590)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR1_REG (HI1822_CPI_DFX_GLB_BASE + 0x594)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR2_REG (HI1822_CPI_DFX_GLB_BASE + 0x598)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR3_REG (HI1822_CPI_DFX_GLB_BASE + 0x59C)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR4_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A0)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR5_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A4)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR6_REG (HI1822_CPI_DFX_GLB_BASE + 0x5A8)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR7_REG (HI1822_CPI_DFX_GLB_BASE + 0x5AC)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR8_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B0)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR9_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B4)
#define HI1822_CPI_DFX_GLB_CPI_RAM_ECC_MULTI_ERR_ADDR10_REG (HI1822_CPI_DFX_GLB_BASE + 0x5B8)
#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C0)
#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C4)
#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED2_REG (HI1822_CPI_DFX_GLB_BASE + 0x5C8)
#define HI1822_CPI_DFX_GLB_IPUSH_RESERVED3_REG (HI1822_CPI_DFX_GLB_BASE + 0x5CC)
#define HI1822_CPI_DFX_GLB_GLB_CPI_UNCRT_ERR_CODE0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D0)
#define HI1822_CPI_DFX_GLB_GLB_CPI_UNCRT_ERR_CODE1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D4)
#define HI1822_CPI_DFX_GLB_GLB_CPI_CRT_ERR_CODE0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5D8)
#define HI1822_CPI_DFX_GLB_GLB_CPI_CRT_ERR_CODE1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5DC)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG0_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E0)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG1_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E4)
#define HI1822_CPI_DFX_GLB_DWQE_BUF_DBG2_REG (HI1822_CPI_DFX_GLB_BASE + 0x5E8)
#define HI1822_CPI_DFX_GLB_ICTL_RX_MWR_TLP_PASS_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F0)
#define HI1822_CPI_DFX_GLB_ICTL_RX_MWR_TLP_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F4)
#define HI1822_CPI_DFX_GLB_ICTL_RX_MRD_TLP_PASS_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5F8)
#define HI1822_CPI_DFX_GLB_ICTL_RX_UNS_NP_TLP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x5FC)
#define HI1822_CPI_DFX_GLB_PCIE_ICTL_SOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x600)
#define HI1822_CPI_DFX_GLB_PCIE_ICTL_EOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x604)
#define HI1822_CPI_DFX_GLB_ICTL_IPUSH_SOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x608)
#define HI1822_CPI_DFX_GLB_ICTL_IPUSH_EOP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x60C)
#define HI1822_CPI_DFX_GLB_GLB_MB_GRP_TX_REQ_REG (HI1822_CPI_DFX_GLB_BASE + 0x610)
#define HI1822_CPI_DFX_GLB_GLB_MB_IN_GRP_TX_REQ_REG (HI1822_CPI_DFX_GLB_BASE + 0x614)
#define HI1822_CPI_DFX_GLB_GLB_MB_GRP_GRANT_REG (HI1822_CPI_DFX_GLB_BASE + 0x618)
#define HI1822_CPI_DFX_GLB_GLB_MB_IN_GRP_GRANT_REG (HI1822_CPI_DFX_GLB_BASE + 0x61C)
#define HI1822_CPI_DFX_GLB_GLB_MB_TX_START_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x620)
#define HI1822_CPI_DFX_GLB_GLB_MB_TX_ILLEGAL_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x624)
#define HI1822_CPI_DFX_GLB_GLB_MB_TX_ILLEGAL_CODE_REG (HI1822_CPI_DFX_GLB_BASE + 0x628)
#define HI1822_CPI_DFX_GLB_GLB_MB_FSM_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x62C)
#define HI1822_CPI_DFX_GLB_DFX_DPATH_O_HISTORY_REG (HI1822_CPI_DFX_GLB_BASE + 0x630)
#define HI1822_CPI_DFX_GLB_DFX_DPATH_O_STATUS_REG (HI1822_CPI_DFX_GLB_BASE + 0x634)
#define HI1822_CPI_DFX_GLB_ICTL_INBD_FIFO_STS_REG (HI1822_CPI_DFX_GLB_BASE + 0x638)
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_INC_CFG_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x640) /* non-MAC Timestamp timer configuration */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_CALIBRATION_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x644) /* non-MAC Timestamp timer calibration */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA0_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x648) /* non-MAC Timestamp timer write data 0 */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA1_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x64C) /* non-MAC Timestamp timer write data 1 */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_WR_DATA2_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x650) /* non-MAC Timestamp timer write data 2 */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA0_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x654) /* non-MAC Timestamp timer read data 0 */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA1_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x658) /* non-MAC Timestamp timer read data 1 */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_RD_DATA2_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x65C) /* non-MAC Timestamp timer read data 2 */
#define HI1822_CPI_DFX_GLB_NON_PTP_TS_UP_EN_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x660) /* non-MAC Timestamp timer update enable */
#define HI1822_CPI_DFX_GLB_NON_PTP_DSTR_CFG_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x664) /* non-MAC Timestamp distribute configuration */
#define HI1822_CPI_DFX_GLB_PCIE_PENDING_TAG_REQ_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x670) /* 接收来自PCIe的数目 */
#define HI1822_CPI_DFX_GLB_ICTL_SND_ERR_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x674)         /* 发送给PCIe AER的数目 */
#define HI1822_CPI_DFX_GLB_ICTL_RX_CPLD_TLP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x678)
#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x680)
#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x684)
#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x688)
#define HI1822_CPI_DFX_GLB_ICTL_RX_TLP_ERR_CODE_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x68C)
#define HI1822_CPI_DFX_GLB_NORM_DBL_RX_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x690)
#define HI1822_CPI_DFX_GLB_NORM_DBL_FORCE_DROP_REG (HI1822_CPI_DFX_GLB_BASE + 0x694)
#define HI1822_CPI_DFX_GLB_DWQE_RX_BUF_BGN_REG (HI1822_CPI_DFX_GLB_BASE + 0x698)
#define HI1822_CPI_DFX_GLB_DWQE_ILLEGAL_DROP_CNT_REG (HI1822_CPI_DFX_GLB_BASE + 0x69C)
#define HI1822_CPI_DFX_GLB_DWQE_DBL_FORCE_DROP_NO_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A0)
#define HI1822_CPI_DFX_GLB_DWQE_DBL_FORCE_DROP_AFT_API_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A4)
#define HI1822_CPI_DFX_GLB_AEQ_FSM_DBG_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x6A8)
#define HI1822_CPI_DFX_GLB_CEQ_FSM_DBG_STATE_REG (HI1822_CPI_DFX_GLB_BASE + 0x6AC)
#define HI1822_CPI_DFX_GLB_GLB_UCPU_MSI_FUNC_IDX_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x6B0) /* the function index when ucpu access CSRs in the INT_CTL */
#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_CTL_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x6B4) /* the control register to measure the inbound itf */
#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x6B8) /* the result for the window detect for the mode */
#define HI1822_CPI_DFX_GLB_PCIE_INBD_ITF_WIND_TLP_CNT_REG \
    (HI1822_CPI_DFX_GLB_BASE + 0x6BC) /* the result for the window detect for the TLP */
#define HI1822_CPI_DFX_GLB_GLB_DBG_CNT_DBL_GRP_EN_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C0)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_TIMER_CFG_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C4)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CFG_PORT01_REG (HI1822_CPI_DFX_GLB_BASE + 0x6C8)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CFG_PORT23_REG (HI1822_CPI_DFX_GLB_BASE + 0x6CC)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT0_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D0)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT1_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D4)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT2_REG (HI1822_CPI_DFX_GLB_BASE + 0x6D8)
#define HI1822_CPI_DFX_GLB_GLB_DBL_CRD_CNT_PORT3_REG (HI1822_CPI_DFX_GLB_BASE + 0x6DC)

#endif // CPI_DFX_GLB_REG_OFFSET_H
